1. Field of the Invention
The present invention relates to a phase locked loop (PLL). More particularly, the present invention relates to a fast locking PLL that has a relatively faster locking time.
2. Description of the Related Art
A PLL is a basic architecture used for generating an internal clock signal in an application-specific integrated circuit (ASIC) and a system-on-chip (SOC), and is widely used for synchronization with an input signal.
FIG. 1 is a schematic block diagram illustrating a conventional PLL.
Referring to the PLL 100, a phase frequency detector (PFD) 10 compares a phase difference of a reference signal CKin and an output signal CKout of the divider 50. The output of PFD 10 drives a charge pump 20, and the charge pump 20 drives a loop filter 30 connected to the VCO 40. The VCO 40 generates a variable frequency signal CKvco in response to a control voltage Vctl of the loop filter 30. The VCO 40 provides the divider 50 with the variable frequency signal CKvco. The divider 50 provides the PFD 10 with the output signal CKout by dividing the variable frequency signal CKvco.
FIG. 2A is a graph illustrating an output voltage of an ideal phase frequency detector (PFD) in accordance with a phase difference of an ideal PFD. FIG. 2B is a graph illustrating an output voltage of an actual PFD in accordance with a phase difference of an actual PFD.
Referring to FIG. 2A, an ideal PFD has a linear region at an interval between −2π and 2π of a graph illustrating the output voltage of the PFD in accordance with a phase difference. Referring to FIG. 2B, an actual PFD such as the conventional PFD 100, however, has a missing edge that misses a phase difference between the reference signal and the output signal. Accordingly, the PLL 100 has a longer locking time as a width of the missing edge increases.
FIG. 3 is a timing diagram illustrating transitions of various signals of the conventional PFD 100. Referring to FIG. 3, the up-signal UP does not follow the reference signal CKin in the region of the missing edge 310.